1. Field of the Invention
The present invention relates to a method for forming a storage node contact, and in particular to a method for forming a storage node contact which forms an artificial void between bit lines among the processes for forming a contact of a semiconductor device in a COB(Capacitor Over Bitline) structure of the semiconductor device.
The present invention also relates to a method for forming a storage node contact in which a margin between a word line and a bit line can secure more widely since the size of the mask forming a capacitor is formed smaller than the conventional art.
2. Description of the Background Art
As the degree of integration of semiconductor device becomes higher, a design rule of the device is being contracted and a process margin is being reduced. In the case of DRAM (Dynamic Random Access Memory) especially, as the study of which progresses toward development of products at the Gigabits level, the importance of a design rule or a process margin in the fabricating process is being recognized and eventually, they affect the operational characteristics of the device. Particularly, since a capacitor for use in DRAM is required to secure a cell capacitance larger than a predetermined capacity within a limited area to enable normal input/output of data or to obtain refresh characteristics, a storage node of the capacitor has a complicated three-dimensional structure and its height also increases. Accordingly, the contraction of the design rule and the reduction of the process margin in a capacitor for DRAM are regarded as constraints more serious than they are in any other memory device or element.
In order to overcome the above problems and to secure a sell capacitance of a level higher than a predetermined capacity, capacitors of various structures have been proposed, that are classified largely into three types; trench-type capacitor, stack-type capacitor and combination-type capacitor which properly combines the former two types of capacitors. Among them, capacitor of a stack-type structure is being widely used because of its comparatively fewer difficulties in fabricating process as well as the easiness in geometrically increasing an effective area.
COB (Capacitor Over Bit line) structure, a stack-type capacitor mentioned above, is fabricated in an order which is reverse to that of the conventional structures. Namely, a contact hole, hereinafter referred to as a bit line contact hole, that connects a bit line and a drain of a lower cell is formed first. Thereafter, conductive material is deposited on the entire surface of the substrate, then a bit line is formed by photo etching, and after depositing an interlayer insulating layer thereon, a storage node contact hole is formed, by having the interlayer insulating layer penetrated, to connect a lower conductive layer, i.e., a source of a cell transistor. The COB structure is then completed by finally depositing a conductive layer on the substrate, photo etching, and forming a storage node. The above-mentioned COB structure is cable of excluding a design rule regarding bit line contact hole when forming the capacitor, and thus has greatly contributed to increasing effective area of a storage node.
In a conventional art, a method for forming a contact will be described with reference to the accompanying drawings as follows.
FIGS. 1a to 1c are views illustrating sequentially processes for forming a storage node contact in accordance with the conventional art.
As shown in FIG. 1a, a bit line 112 is formed on a semiconductor substrate 110 having a predetermined lower structure. An upper part and a sidewall of the bit line 112 are covered with a hard mask 114 and a spacer 116, respectively.
As shown in FIG. 1b, a first conductive layer for forming a sacrificed insulation pad 120 is deposited on the entire surface of the resultant material and thereafter photo etched, thereby forming a sacrificed insulation pad 120.
As shown in FIG. 1c, an interlayer insulation layer 130 is deposited on the resultant material and thereafter a planarization process is performed. Continuously, a contact hole 132 is formed on a position of the interlayer insulation layer 130 corresponding to a position existing the sacrifice insulation layer 120 and thereafter a predetermined pattern, for example a conductive layer 140 for forming a storage electrode of a capacitor, is formed on the entire surface of the resultant material.
However, as mentioned above. when a junction part of the storage node is formed by embedding the sacrifice insulation pad 120 to the contact hole 132, an entire step difference is increased, so that the etching of the bit line is not performed in one""s own way because of the increase of the entire step difference when performing a dry etching for forming a deep junction part. That is, according to the conventional art, there are several disadvantages that a formation of the storage is very difficult, that is, the fabrication processes are very difficult and the yield is reduced.
Also there are further disadvantages that although a void having reproducibility, not affected by a wiring structure, is formed and a layer having a bad step coverage characteristic is used, the residual layer on the sidewall and the lower portion of the junction part can not be removed completely.
It is an object of the present invention to provide a method for forming a storage node contact in which the inorganic SOG layer is deposited and heat-treated after forming a bit line having a conductive layer and a spacer on the semiconductor substrate and there is an advantage that the density of the organic SOG layer embedded between the bit lines become lower than that of the organic SOG layer stacked on the bit lines. When performing the wet etching process, the speed for etching the inorganic SOG layer between the bit lines become very rapid, so that an artificial void is formed and an etching become very easier when performing a dry etching process of a deep storage node contact junction part.
In order to achieve the above-described object of one aspect of the present invention, a method for forming a storage node contact comprises the steps of: forming a bit line on a semiconductor substrate having a predetermined lower structure; depositing an inorganic SOG oxide layer on the resultant material and executing a thermal process; depositing a photo resist layer on the inorganic SOG layer and then forming a photo resist pattern in order to intercept a part for forming a storage node contact and open the other part, thereafter etching the inorganic SOG oxide layer; forming an artificial void by removing the inorganic SOG oxide layer filled between the bit lines by a wet etching process; depositing a HDP oxide layer on the- resultant material for isolating the storage node in order not to be embedded the void of the inorganic SOG oxide layer; performing a planarization process of the resultant material by a CMP process and thereafter depositing a photo resist layer selectively and executing a masking etching process for forming a storage node contact, thereby forming the storage node contact connected to a plug poly.
According to the present invention, there is an advantage that the density of the organic SOG layer embedded between the bit lines become lower than that of the organic SOG layer stacked on the bit lines and when performing the wet etching process, the speed for etching the inorganic SOG layer between the bit lines become very rapid, so that an artificial void is formed. As a result, when performing a wet etching process of a deep storage node contact part, the etching can be executed in a short time by using the void, which is formed by an insufficiency oxidation.